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Download Designing Digital Systems With SystemVerilog written by Brent E. Nelson in PDF format. This book is under the category Computers and bearing the isbn/isbn13 number 1980926298; 148380002/9781980926290. You may reffer the table below for additional details of the book.

## Description

* Designing Digital Systems With SystemVerilog; (PDF) *is for a university sophomore/freshman course on digital logic and digital systems design. Furthermore; the SystemVerilog language is intertwined throughout the text; providing both new learners and also existing digital logic designers an introduction to the SystemVerilog language and its use for designing digital systems.

**NOTE: The product includes the ebook; Designing Digital Systems With SystemVerilog in PDF. No access codes are included.**

## Additional information

book-author | Brent E. Nelson |
---|---|

publisher | Independently published |

file-type | |

pages | 340 pages |

language | English |

isbn10 | 1980926298; 148380002 |

isbn13 | 9781980926290 |

## Table of contents

Table of contents :

Introduction to Digital Systems Design

Digital vs. Analog

Positional Number Systems

Digital vs. Analog Continued

Analog vs. Digital Data Storage

Analog vs. Digital Data Processing

Analog vs. Digital – A Summary

Combinational vs. Sequential Digital Circuits

Chapter Summary

Number Systems and Binary Encodings

Positional Number Notation

Conversion from Decimal to Other Bases

Hexadecimal (Base-16) Numbers

Binary-Coded Decimal

Other Codes

ASCII Codes

Gray Codes

Chapter Summary

Exercises

Signed Number Representations, Negation, and Arithmetic

Addition of Unsigned Numbers

Overflow in Unsigned Addition

Signed Numbers: Sign-Magnitude

Negating Sign-Magnitude Numbers

Signed Numbers: 2’s Complement

Sign-Extension

Negating a 2’s Complement Number

Adding 2’s Complement Numbers

Subtracting 2’s Complement Numbers

Signed Numbers: 1’s Complement

Summary — Number representations

More on Overflow and Underflow

Detecting and Handling Overflow and Underflow – Some Ideas

Chapter Summary

Exercises

Boolean Algebra and Truth Tables

Introduction to Boolean Algebra and Truth Tables

Truth Tables for Arbitrary Functions

Converting Truth Tables to Boolean Equations

Converting Boolean Functions to Truth Tables

Boolean Identities and Theorems

Single-Variable Theorems

Two-Variable Theorems

Commutative, Associative, and Distributive Theorems

The Simplification Theorems

The Consensus Theorems

Summary of the Boolean Theorems

Chapter Summary

Exercises

Gates

Basic Gate Types

Transistors – The Building Blocks of Gates

Building An Inverter Using FET’s

Other 2-Input Gates

NAND Gates

NOR Gates

An Exclusive-OR Gate

An Equivalence Gate

Multi-Input Gates

Alternative Gate Symbology

Multi-Level Logic

Speed of Operation

Circuit Area

Speed and Area Comparisons

Factoring and Multiplying Out

Chapter Summary

Exercises

Boolean Algebra – Part II

Inverting a Function – DeMorgan’s Rules

Sum-of-Products and Product-of-Sums Forms

Canonical Forms – Minterm Expansion and Maxterm Expansion

Boolean Minimization

What is a Minimal Form for an Expression?

Minimization By Applying Boolean Theorems

Proving Equalities Using Boolean Theorems

Incompletely Specified Functions and Boolean Minimization

Summary of Boolean Minimization

Chapter Summary

Exercises

Gates – Part II

NAND-NAND and NOR-NOR Logic

Functionally Complete Logic Sets

Gate Symbology — Matching Bubbles

Bubble Matching and Reconvergent Fanout

Chapter Summary

Exercises

An Introduction to Gate-Level Design Using SystemVerilog

Three Important Rules Regarding Designing using an HDL For Digital Systems Design

Levels of Design Abstraction in SystemVerilog

Basic Structural SystemVerilog Design

Structural Gate Instantiations are Concurrent Statements

Declaring Wires in SystemVerilog

CAD Tool Design Flow

Chapter Summary

Exercises

Gate-Level Arithmetic

A Hardware Adder

An Adder/Subtracter Module

Adding and Subtracting 1’s Complement and Sign-Magnitude Numbers

Chapter Summary

Exercises

Higher Level Building Blocks: Multiplexers, Decoders, and Lookup Tables

Introduction

Multiplexers

A 4:1 Multiplexer

Multi-Bit Wires in Schematics

Using Multiplexers for Logic

Decoders

When to Use Multiplexers and Decoders

Read-Only Memories (Lookup Tables)

Chapter Summary

Exercises

Continuing on With SystemVerilog – Hierarchical Design, Constants, and Multi-Bit Signals

Creating Hierarchy Via Structural Instantiation

Semantics of Module Instantiation

Specifying Constants in SystemVerilog

Accessing Bits of Multi-Bit Wires in SystemVerilog

More on Naming – Modules, Instance Names, and Wires

Hierarchical Design Flow

Chapter Summary

Karnaugh Maps

Truth Tables to KMaps

Three-Variable KMaps

Minterm and Maxterm Expansions and KMaps

Circling More Than Two 1’s

Four-Variable KMaps

Plotting a Boolean Equation on a KMap

Deriving Product of Sum Expressions from KMaps

Solving a KMap With Don’t Cares

Finding Optimal Solutions Using KMaps

A Worked Example — A BCD to 7-Segment Converter

Chapter Summary

Exercises

Gate Delays and Timing in Combinational Circuits

Introduction

Basic Gate Delays

Critical Path Analysis

Levels of Detail in Timing Analysis

Input Glitches, Timing, and Gate Behavior

A Pulse Generator

False Outputs

False Outputs and Hazards: Summary

Gate Delay Variations

Gate Delay Variation: Summary

Chapter Summary

Exercises

Dataflow SystemVerilog

A Basic 2:1 MUX

Dataflow Operators

Bitwise vs. Logic Operators

Reduction Operators

Concatenation and Replication Operators

Operator Precedence

Matching Wire Widths

Example – a 2:4 Decoder

Parameterization in Dataflow SystemVerilog

Mixing Dataflow and Structural SystemVerilog Design

SystemVerilog and Arithmetic

Chapter Summary

Exercises

Latches and Flip Flops

Bistability and Storage: The SR Latch

The Gated Latch

The Master/Slave Flip Flop

Rising-Edge Triggered Flip flop

Timing Characteristics Of Flip Flops

Flip Flops With Additional Control Inputs

A Note on Timing Diagrams

A Note on Metastability

Chapter Summary

Exercises

Registers and RTL-Based Design

Flip Flop-Based Registers

Loadable Registers – First Attempt

Loadable Registers – The Correct Method

Shift Registers

Mini Case Study: An Accumulator-Based Averaging Circuit

An Introduction to Register Transfer Level (RTL) Design

The Loadable Register of Figure 16.4

The Clearable Up Counter of Figure 16.7

The Shift Register of Figure Figure 16.9

The Averaging Circuit of Figure 16.11

More Complex Examples of RTL

Chapter Summary

Exercises

Behavioral SystemVerilog for Registers

Introduction to Behavioral SystemVerilog

The always_ff Block

Shift Register Design Using Behavioral SystemVerilog

The Semantics of the always_ff Block

Chapter Summary

Exercises

Modeling Combinational Logic Using Behavioral SystemVerilog

Combinational always Blocks

The Problem With Latches

Avoiding Latches When Using case Statements

Summary: Avoiding Latches in always_comb Blocks

Mapping SystemVerilog Programs to a Specific Technology

Chapter Summary

Exercises

Memories

Introduction

Register Files

Register File Design Using Behavioral SystemVerilog

Multi-Ported Register Files

Multi-Ported Register File Design using SystemVerilog

Multi-Ported Register Files With Bypass

Larger Memories

Read-Only Memories (ROM)

Consulting Tool Documentation

Chapter Summary

Exercises

Simple Sequential Circuits: Counters

A Two-Bit Binary Counter

A Two-Bit Gray Code Counter

A Counter Example With An Incomplete Transition Table

Counters With Static Output Signals

Delay Characteristics of Counters

Moore Output Delay Characteristics of Counters

Counters With Additional Inputs

Mealy (Dynamic) Outputs

Mealy vs. Moore Outputs

Counter Design Using Behavioral SystemVerilog

Chapter Summary

Exercises

State Graphs

An Example State Graph

State Graphs For Counters With Inputs

State Graphs For Counters With Multiple Inputs

Design Procedure Using State Graphs

Representing Counter Outputs in State Graphs

Moore (Static) Outputs

Mealy (Dynamic) Outputs

Properly Formed State Graphs

Chapter Summary

Exercises

Finite State Machines

A Simple State Machine – A Sequence Recognizer

A Continuous ‘011’ Detector – Moore Version

A Continuous ‘011’ Detector – Mealy Version

Finite State Machine Example – Car Wash Controller

Implementation Details

A Car Wash With Two Different Wash Settings

Resetting State Machines

Completeness and Conflicts in State Graphs Revisited

Chapter Summary

Exercises

State Machine Design Using SystemVerilog

SystemVerilog Features for Coding State Machines

State Machine Coding Styles

A Defensive Coding Style for Finite State Machines

Chapter Summary

Asynchronous Input Handling

Asynchronous Inputs and Metastability

An Example Asynchronous Input Problem

Synchronizing Asynchronous Inputs – The Easiest and Preferred Approach

Hazard Free Design Combined With Adjacent State Encodings – Another Approach (Advanced Topic)

Adjacent State Encodings – A Partial Solution

False Outputs and Hazards

The Complete Solution

Chapter Summary

Exercises

Field Programmable Gate Arrays (FPGAs) – An Introduction

Lookup Tables – Universal Function Generators

Mapping Larger Combinational Circuits to LUTs

Mapping Gate-Level Circuits to LUTs

FPGA Logic Elements

Global FPGA Architecture

A Mapping Example

Configuring an FPGA Device

Configuring a LUT

Configuring the Fabric

More Advanced FPGA Architectures

Configurable Input/Output

Configuration Technology

Carry/Cascade Chains

Programmable Interconnections

Segmented and Hierarchical Routing

Clustered LEs

Embedded Functional Units

FPGA vs. ASIC Technology

Chapter Summary

Exercises

Case Study – Debouncing Switches and Detecting Edges

Debouncing a Switch

Design of the Debouncer Using SystemVerilog

A One-Shot (Also Known as Pulse Generator)

Exercises

Case Study: A Soda Machine Controller

Step 1 – Understand the Complete System Requirements and Organization

Understanding the Coin Mechanism

Understanding the Dispense Module

Understanding the User Interface

Step 2: Determine a System Architecture

Step 3 – Design the System Parts

Design of the Timer Subsystem

Design of the Keypad Interface Subsystem

Design of the Central Control Subsystem

Design of the Accumulator

Design of the Central Control Subsystem State Machine

A Complete and Conflict-Free State Graph

Implementing the State Machine Using SystemVerilog

Asynchronous Inputs, Adjacent State Encodings, and Glitch-Free Outputs

Summary

Exercises

Case Study: The Design of a UART

UART Protocol Design

Protocol Summary

Designing the UART

Design of a UART Transmitter

Host-UART Handshaking

The Transmitter Datapath

The Transmitter Control Section

An Alternate Transmitter Coding Style

Design of a UART Receiver

Summary

SystemVerilog vs. Verilog

SystemVerilog vs. Verilog

Data types

The logic Variable Type

Enumerated Types

Enhanced always Blocks

Verilog, SystemVerilog, and VHDL Interoperability

Moving Forward

ASCII Table

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